The present invention generally relates to semiconductor circuits and more particularly to a buffer circuit for logic level conversion.
In the digital signal processing, there often arises a case where a logic signal produced by a first semiconductor processor with a first logic level and amplitude has to be processed by a second semiconductor processor that operates based on the logic signal having a different logic level and amplitude. Such a situation arises, for example, when an output logic signal produced by an ECL circuit is processed by a circuit that employs the HEMT or vice versa. In such a case, it is necessary to interpose a buffer circuit between the first and second semiconductor circuits for logic level conversion such that a compatibility is achieved in the logic level of the signals.
FIGS. 1 and 2 show typical conventional buffer circuits wherein the circuit 10 of FIG. 1 has a level shift circuit 20 of the source-follower type combined with an inverter 30 having the DCFL construction, while the circuit 40 of FIG. 2 has a differential construction of the SCFL circuit.
Referring to FIG. 1, the level shift circuit 20 has a pair of depletion mode FETs 21 and 22 connected in series between the ground and a voltage source VEE1 that may provide a negative voltage of -3.6 volts, while the inverter circuit 30 has a depletion-mode FET 31 and an enhanced mode FET 32 connected in series between the ground and a second voltage source VEE2 that may provide a negative voltage of -2.0 volts. Thereby, the source of the FET 21 that is connected to the drain of the FET 22, is connected further to the gate of the FET 32. Further, the buffer circuit 10 has an input terminal IN connected to the gate of the FET 21 and an output terminal OUT connected to the source of the FET 31 that is connected to the drain of the FET 32. The FET 22 has the gate connected to its source and the FET 31 has the gate connected to is source.
In operation, the buffer circuit 10 is supplied with an ECL signal that assumes -1.5 volts in the low level state and -0.6 volts in the high level state. In response to the low level state of the input signal, the FET 21 is turned OFF and a voltage of -1.8 volts appears at a node .sub.m between the FET 21 and FET 22, and the FET 32 is turned OFF. Thereby, an output voltage at the output terminal OUT takes a value of about zero volt. On the other hand, when the high level input signal is supplied at the input terminal IN, the FET 21 is turned ON and a voltage of about -0.9 volts appears at the node .sub.m. In response to this, the FET 32 is turned ON and an output voltage of about -2.0 volts appears on the output terminal OUT. Thereby, a desired level shift of the logic signal is achieved. In this circuit, the desired level shift is mainly achieved by the FET 21.
In this conventional buffer circuit 10, however, there is a problem in that, because of the back gate effect or so-called side gate effect, caused by the large negative voltage of -3.6 volts, the drain current of the FET 21 is changed from its designed value. Thereby, the voltage supplied to the inverter 30 is changed as shown in FIG. 3. In FIG. 3, the continuous line represents the designed input-output characteristic curve while the broken line represents the actual input-output characteristic. As can be seen in FIG. 3, the threshold voltage of the buffer circuit 10 shifts as indicated by the arrow from TH to TH'. When this occurs, the output logic signal of the buffer circuit 10 no longer represents the logic state of the input signal.
In the circuit of FIG. 2, on the other hand, the buffer circuit 40 has the differential SCFL construction, wherein a first branch circuit including a depletion mode FET 41 and an enhanced mode FET 42 connected in series and a second branch circuit including a depletion mode FET 43 and an enhanced mode FET 44 connected in series, are connected parallel with each other between the ground and a voltage source VEE1 via a depletion mode FET 45 that forms a common constant current source for the both branches. The gate of the FET 41 is connected to its source, the gate of the FET 43 is connected to its source, and the gate of the FET 45 is connected to its source. Thereby, the FETs 41, 43 and 45 are operated in the saturated region and act as the constant current source. To the gate of the FET 42, the input signal is supplied via an input terminal IN. Further, the FET 44 receives at its gate a reference signal V.sub.REF. The output signal is obtained thereby at the source of the FET 41.
In operation, the voltage source VEE1 provides the negative voltage of -3.6 volts, and a voltage corresponding to the difference between the current flowing through the FETs 41 and 42 and the current flowing through the FETs 43 and 44, appears at the output terminal OUT in response to the input voltage supplied to the gate of the FET 42 via the input terminal IN. It should be noted that the FET 44, corresponding to the mirror image of the FET 42, is supplied with the constant reference voltage V.sub.REF.
This circuit, too, shows the side gate effect because of the large negative voltage at the voltage source VEE1. As the circuit construction of the buffer circuit 40 is generally symmetric in the both branches, the side gate effect appears in the both FETs 42 and 44. Thereby, the change in the threshold voltage of the circuit 40 can be avoided.
FIG. 4 shows the input-output characteristic of the buffer circuit 40. In this drawing, too, the continuous line represents the designed input-output characteristic while the broken line represents the actual input-output characteristic.
As can be seen, the operational point or threshold level TH of the circuit 40 is determined as an intersection of a curve BR1 representing the input-output characteristic of the first branch and a curve BR2 representing the input-output characteristic of the second branch. When the side gate effect appears, both curves BR1 and BR2 shift in the downward direction as shown, and little change occurs in the threshold level TH. However, in terms of the level L representing the output logic level of the circuit 40, the threshold level of the buffer circuit that distinguishes the high level state from the low level state does change, from the level TH to the level TH' as illustrated. It should be noted that the output of the buffer circuit 40 is obtained from the first branch as illustrated. Thereby, the circuit 4 cannot provide satisfactory operation as the input buffer circuit.